Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology

In the sub-threshold region we can fit the drain current to the following basic exponential model,

$$ I_D =I_S \exp\left( \dfrac{V_{GS}}{\eta V_T}\right) $$

Bench supply \(V_{s1}\) provides the gate-source bias potential \(V_{GS}\). Voltmeter \(V_{m1}\) records the effective gate-source potential at the terminals of \(M_1\). Bench supply \(V_{s2}\) biases the drain of \(M_1\) at \(\simeq 5\) VDC. With \(V_D\) = 5, \(M_1\) is biased into the saturation region for a diverse range of gate drive potentials. A schematic of the test setup is shown in the figure below.

Ammeter \(A_{m1}\) will present a small burden voltage in series with supply \(V_{s1}\). \(A_{m1}\) employs a \(5\Omega\) current shunt resistor for its \( 10 \& 100 \) mA current ranges. Worst case burden in the sub-threshold region is,

$$ V_{BRD} = (0.1)(5) = 500 \text{ mV} $$

With a 100 mA of drain current the drain potential will decline from 5V to 4.5V a 10% reduction in drain bias. Fortunately \( M_1\) has a modest \( \lambda \) in the sub-threshold region.

The results of sweeping \(V_{GS}\) of a sample DUT at a fixed \(V_{DS}\) of 5 V is shown in the figure below.

The log fit results in the following exponential function of \(V_{GS}\),

$$ I_D =34.5\text{ fA } \exp\left( \dfrac{V_{GS}}{58 \text{ mV}}\right) $$

Every 10x increase in drain current in the sub-threshold region requires an additional gate drive voltage of,

$$ \Delta V_{GS} = \eta V_T \log(10) = 134 \text{ mV/dec} $$

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Here the panel is constructed with N equal diode junctions all sharing one common photo current source \(I_S\).

We can attempt to solve the load I-V relationship by either applying a know voltage source \(V_L\) or apply a know load current \(I_L\) and then proceed to solve the available load current or load voltage. In this blog post we will apply a know load voltage \(V_L\) and solve for the available load current \(I_L\).

We begin naming the internal voltage across the series string of diodes node \(V_X\). We then apply KCL at \(V_X\) as,

$$ -I_S + \dfrac{V_X}{R_P} + I_o \exp(\dfrac{Vx}{N\eta V_T}) + \dfrac{V_X-V_L}{R_S} = 0$$

Solution of the above equation requires use of the lambert-w function and is far from trivial. We may also solve the equation numerically in Matlab. Sample Matlab code is shown below,

% Define anonymous function based on KCL at internal node Vx f = @(Vx) (Vx-VL)/Rs + Io*exp(Vx/(N*eta*VT)) + Vx/Rp - Is; % solve first root Vx = fzero(f,[min(0,VL) 1*eta*N]); % Output Load Current IL = (Vx - VL)/Rs;

Suppose we wish to determine the impact of panel series resistance on the available output power. In the sample code below we define panel parameters and solve for the available load current for some load voltage \(V_L\) and panel series resistance \(R_S\). For simplicity the iteration of panel voltage and series resistance is omitted.

k = 1.3806e-23; q = 1.602e-19; Is = 0.1; N = 4; Io = 1e-10; eta = 2; T = 300; VT = k*T/q; Rp = 100e3; Rs = 1e-3; % Define anonymous function based on KCL at internal node Vx f = @(Vx) (Vx-VL)/Rs + Io*exp(Vx/(N*eta*VT)) + Vx/Rp - Is; % Solve first root Vxi = fzero(f,[min(0,VL) 1*eta*N]); % Output Load Current IL = (Vxi - VL)/Rs;

The results from the simulation code above are shown in the figure below.

We can first note that the panel open-circuit voltage is unaffected by series resistance (this makes sense as with no load current there is no voltage drop across the series resistance \(R_S\)). A second plot focusing on the MMP of the various simulation runs is shown in the figure below.

The maximum point for each simulation run is shown in the table below.

Rs [Ohms] | Pmax [mW] | Vp [V] | Ip [mA] | Vx [V] |
---|---|---|---|---|

0 | 259 | 2.78 | 93.0 | 2.78 |

2 | 242 | 2.62 | 92.1 | 2.81 |

4 | 225 | 2.47 | 91.0 | 2.83 |

6 | 209 | 2.33 | 89.6 | 2.87 |

8 | 193 | 2.20 | 87.8 | 2.90 |

10 | 178 | 2.08 | 85.5 | 2.93 |

We can observe that to a first order the decline in output power is approximately equal to the \(I^2R\) losses of the series resistor \(R_S\).

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The dashed outline depicts the formation of one supper-beta pnp transistor. We can note that transistor Q2 is a pre-driver to transistor Q1. To asses the complete forward dc current gain of the darlington pair, we begin by apply KCL at each of the terminals as,

$$ I_C = I_{C1} + I_{C2} $$

$$ I_E = I_{E1} $$

$$ I_B = I_{B2} $$

The forward current gain of the darlington arrangement is then,

\begin{align*}

\beta &= \dfrac{I_C}{I_B} \\

&= \dfrac{I_{C1}+I_{C2}}{I_{B2}} \\

&= \dfrac{\beta_1 I_{B1}+ \beta_2 I_{B2}}{I_{B2}} \\

&= \dfrac{\beta_1 I_{E2}+ \beta_2 I_{B2}}{I_{B2}} \\

\end{align*}

The emitter current of Q2 is,

$$ I_{E2} = I_{B2} + \beta_2 I_{B2} = (1+\beta_2)I_{B2} $$

Substitution back into the beta relation yields,

\begin{align*}

\beta &= \dfrac{\beta_1 (1+\beta_2) I_{B2} + \beta_2 I_{B2}}{I_{B2}} \\

\beta &= \beta_1\beta_2 + \beta_1 + \beta_2 \\

\end{align*}

For \( \beta_1 >> 1\) and \( \beta_2 >> 1\) the forward DC current gain simplifies to,

$$ \beta \simeq \beta_1 \beta_2 $$

Hence, the darlington pair behaves just like a single bipolar transistor with the relation,

$$ I_C = \beta I_B $$

A sample darlington transistor arrangement is constructed with an MPS4250 as a pre-driver and a MJE15029 power transistor. The relevant component specifications are as follows,

MPS4250: \(\beta = 450\), \(V_{cemax} = 40 \text{VDC}\)

MJE15029: \(\beta = 150\), \(V_{cemax} = 120 \text{VDC}\)

A schematic of the test setup is shown in the figure below.

Transistors Q1 and Q2 form a darlington transistor, whose emitter potential is referenced to bench power supply \(V_S1\). A base current is developed by biasing a series resistor \(R_B\) at a potential below \(V_E\) by bench supply \(V_{s2}\). Since the base current is expected to be below one 1 uA, base current is measured by also employing bias resistor \(R_B\) as a current shunt resistor. The base current shunt is sampled by voltmeter \(V_m1\) while being configured for hi-z input impedance.

Ammeter \(A_{m1}\) employs an internal 5 \(\Omega\) current shunt resistor for 10 mA and 100 mA measurement scales. The potential at \(V_C\) is then,

$$ V_C = R_{Am1} I_C = 5 I_C $$

At a full scale test current of 100 mA, \(V_C\) rises to 500 mV and consequently the DUT’s \(V_{CE}\) declines to,

$$ V_{CE} = V_C – V_E = -V_{s1} + 5I_C$$

Bench supply \(V_{s2}\) is programmaticly stepped from 0 to 12 VDC, which in turn steps the base current from 0 nA to approx 1 uA. With the exact figure determined by voltmeter \(V_{m1}\). The resulting collector current is sampled by ammeter \(A_{m1}\). The process is repeated for 4 \(V_{CE}\) bias voltages.

The base and collector currents for 4 {V_CE} bias runs is shown in the figure below.

Approximately speaking, with a 1 uA base current the collector current ranges from 70 mA to 120 mA, depending on \(V_{CE}\) and junction temperature.

A plot of the forward current gain \(\beta\) versus collector current is shown in the figure below.

We can note that the current gain is a function of \(I_C\), \(V_{CE}\), and \(T_J\).

]]>For diode forward voltages \(V_D\) greater than a few \( \eta V_T\), such as 100 mV, the diode equation is approximately equal to,

$$ I_D \simeq I_o exp\left( \dfrac{V_D}{\eta V_T} \right) $$

Applying KCL at the output node of the schematic above yields,

$$ I_D + I_L = I_S $$

$$ I_D = I_S – I_L $$

The forward voltage of the diode can be determined as,

\begin{align*}

V_D &= \ln \left( \dfrac{I_D}{I_o} \right) \eta V_T \\

V_D &= \ln (I_S – I_L)\eta V_T -\ln (I_o)\eta V_T

\end{align*}

The output load power is equal to,

$$ P_L = V_L \cdot I_L $$

Since the output terminals are in parallel to the shunt diode’s terminals the output load voltage is identical to the diode’s forward voltage,

$$ V_L = V_D $$

Hence, the output load power as a function of load current becomes,

$$ P_L = \ln( I_S – I_L )\eta V_T I_L – \ln(I_o)\eta V_T I_L $$

Differentiating the load power with respect to load current yields,

$$ \dfrac{\partial P_L}{\partial I_L} = \dfrac{\eta V_TI_L(-1)}{I_S-I_L} + \ln(I_S-I_L)\eta V_T – \ln(I_o)\eta V_T $$

We can determine the MPP as the the inflection point where \(\partial P_L/\partial I_L\) equals 0, as,

\begin{align*}

\left| \dfrac{\partial P_L}{\partial I_L} \right|_{I_L=I_P} &= 0 \\

\ln \left( \dfrac{I_S – I_P}{I_o} \right)\eta V_T &= \dfrac{ I_P \eta V_T}{I_S – I_P} \\

\end{align*}

We then arrive at the following expression for the MPP load current,

$$\ln \left( \dfrac{I_S – I_P}{I_o} \right) = \dfrac{I_P}{I_S – I_P} \tag{EQ.1} $$

The solution for the load current \(I_L\) which yields the maximum output load power is only a function of the current source \(I_S\) and the diode’s saturation current \(I_o\). The solution of \(\ln(ax)=bx+c\) is non-trivial. Hence, we will attempt to find an approximation for the natural log function. A plot left-hand term of EQ.1 is shown in the figure below.

Here to simplify the solution we will begin by assuming the maximum power point occurs at 0.9 I_s (10% less than a short circuit condition). The natural logarithm can then be approximated as,

$$ \ln \left( \dfrac{I_S – 0.9I_S}{I_o} \right) = \ln \left( \dfrac{0.1I_S}{I_o} \right) $$

Substitution our approximated log term yields,

$$ \ln \left( \dfrac{0.1I_S}{I_o} \right) = \dfrac{ I_P}{I_S – I_P} $$

The approximate MPP load current is then,

$$ I_P = I_S\left( \dfrac{\ln(0.1I_S/I_o)}{1+\ln(0.1I_S/I_o)} \right) $$

The table below provides the approximate MMP load current for a diverse range of source currents \(I_S\) and diode saturation currents \(I_o\).

\(I_S/I_o\) | MPP Current \(I_P\) |
---|---|

\(10^6\) | \(0.920 I_S\) |

\(10^7\) | \(0.933 I_S\) |

\(10^8\) | \(0.942 I_S\) |

\(10^9\) | \(0.949 I_S\) |

\(10^{10}\) | \(0.954 I_S\) |

\(10^{11}\) | \(0.958 I_S\) |

\(10^{12}\) | \(0.962 I_S\) |

The output power of a diode shunted current for an assortment of load and source conditions is shown in the figure below.

Even when the ratio \(I_S/I_o\) varies by over 6 orders of magnitude the MPP load current is only perturbed from \(0.919I_S\) to \(0.961I_S\).

A plot for diode ideality factor \(\eta = 2\) is shown in the figure below.

As shown in the analysis above, the MPP load current is not a function of \(V_T\) or \( \eta \).

The fill factor of a solar cell is defined as,

$$ FF = \dfrac{V_{mp}I_{mp}}{V_{oc}I_{sc}} $$

We have seen that for a diode shunted current source the MPP load current is roughly 92% to 96% of the short-circuit current. Hence the ratio \(I_{mp}/I_{sc}\) is known and relatively constant over a diverse range of illumination currents and junction saturation currents.

During open-circuit conditions, all of the generated photo current is conducted by the shunt diode. At the maximum power point the conducted current through the diode declines to 4% to 8% of the short-circuit current (the rest of the photo current is delivered to the load). We can solve the decline in forward voltage as,

$$ \Delta V_D = \eta V_T \ln\left( \dfrac{I_S}{I_S – I_P} \right) $$

As an illustration consider,

$$ \eta = 1, \;\;\; V_T = 25.2 \text{ mV},\;\;\; I_S = 100 \text{ mA}, \;\;\;I_o = 100 \text{ pA}$$

The MPP load current is then approximately,

$$ I_P \simeq 0.95 I_S $$

$$ \Delta V_D = 25.2 \ln( 1/0.05 ) = 25.2 \ln(20) = 75.5 \text{mV} $$

The current source’s open circuit voltage is,

$$ V_{oc} = 25.2 \ln( 100 \text{ mA} / 100 \text{ pA} ) = 522.2 \text{ mV} $$

$$ V_{mp} = 25.2 \ln( I_D / 100 \text{ pA}) = 25.2\ln(5 \text{ mA}/100 \text{ pA}) = 446.7 \text{ mV} $$

Finally we can determine the fill factor for this example as,

$$ FF = \dfrac{(446.7)(0.95)}{(552.1)(1)} = 0.812 $$

$$ P_{max} = (0.812)V_{oc}I_{sc} $$

The take away from all of this, is, that the load current for maximum output power is approximately equal to 95% of the short-circuit current. Since the ratio of \(I_{mp}/I_{sc}\) is approximately constant, the decline in output voltage \(\Delta V\) from \(V_{oc}\) to \(V_{mp}\) is also a constant number of \( (\eta V_T) \) ‘s.

One could loosely approximate the fill factor of a *single solar cell* as,

$$ FF \simeq \left(\dfrac{V_{oc} – 75\text{ mV}}{V_{oc}}\right) (0.95) $$

Which clearly indicates that the larger the open circuit voltage (either by larger photo current or by a smaller saturation current) the higher the fill factor. A plot of fill factor for a wide range of photo and diode saturation currents is shown in the figure below.

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KCL across the output nodes of the current source yields,

$$ \dfrac{V_L}{R_s} + I_o = I_s $$

$$ V_L = \left( I_s – I_o \right) R_s $$

The power consumed by the load is then simply the current-voltage product as,

\begin{align*}

P_L &= V_L I_L \\

&= \left( I_s – I_L \right) R_s I_L \\

&= R_s \left( I_sI_L – I_L^2 \right) \\

\end{align*}

The output power is a 2nd order function of load current. A normalized graph of load power versus load current when powered by a current source is shown in the figure below.

At some load current \(I_P\) the output power reaches its maximal value and then begins to decline. We can solve for the maximum power point \(P_{max}\) as the point where the first derivative of \(P_L(I_L)\) equals 0.

$$ \dfrac{\partial P_L}{\partial I_L} = I_sR_s -2R_sI_L $$

\begin{align*}

\left| \dfrac{\partial P_L}{\partial I_L} \right|_{I_L=I_P} &= 0\\\\

0 &= I_sRs – 2R_sI_P \\\\

I_P &= \dfrac{I_s}{2} \\\\

\end{align*}

Hence, the maximum load power occurs when the load current equals \( I_s/2\).

It should come as no surprise that a resistive load which consumes the maximum available power is a resistor of \(R_L = R_S\).

The maximum available power is then,

\begin{align*}

P_{max} &= P_L( I_P )\\

&= R_s( I_sI_P – I_P^2 )\\

&= R_s( \dfrac{I_s^2}{2} – \dfrac{I_s^2}{4} )\\

P_{max} &= \dfrac{I_s^2R_s}{4} \\

\end{align*}

Consider a current source with the following parameters,

$$ I_s = 100 \text{ [mA]}\;,\;\;\; R_s = 100 \; [\Omega] $$

A sample spice test jig is shown in the figure below.

Ideal current source \(I_s\) and shunt resistance \(R_s\) form a current source with output resistance \(R_S\). An ideal current source is parametricly swept from \(0\) mA to \(100\) mA as a synthetic load. The results of the simulation are shown in the figure below.

The open-circuit voltage of the current source is \(V_{oc} = I_s R_S = 10 \) VDC. the short-circuit current is \( I_{sc} = I_s = 100 \) mA. The maximum power point occurs at a load current of \(50\) mA, with a corresponding peak load power of \(250\) mW.

The maximum power point as estimated from the analysis above occurs at a load current of,

$$ I_P = \dfrac{I_s}{2} = 50 \text{ [mA]} $$

With a maximum power point of,

$$ P_{max} = \dfrac{I_s^2R_s}{4} = 250 \text{ [mW]} $$

If a solar cell were to appear as a current source with shunt resistance \(R_S\) then its short-circuit current is simply,

$$ I_{SC} = I_S $$

The cells open circuit voltage is,

$$ V_{OC} = I_S R_S $$

The maximum power available from the cell would be,

$$ P_{max} = \dfrac{I_s^2R_s}{4} = \dfrac{V_{OC}I_{SC}}{4} $$

Hence a current source with shunt resistance has a fill factor of 0.25.

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The DAC is swept from code 0 to code 255 and the output of the shunt regulator is recorded. The resulting transfer function of programmable shunt regulator is shown in the figure below.

The integral non-linearity of the system is determined as the residual form a least-squares fit of a first order function. The plot below depicts the system INL, the magnitude is normalized to LSBs.

A worst case INL of 0.24 LSB is observed at the full-scale code (255).

DNL of the system is measured as the difference from 1LSB at each code step.

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The two recommended termination signatures to be used when fast-charging NiCd cells are either negative \(\Delta V\) or positive dT/dt. Thermal detection is more challenging to implement as one requires good thermal contact between a temperature detector and the cell under charge. In the case of negative \(\Delta V\) one already has the cell potential by the same contacts being used to apply the charge current. However, one requires sufficient measurement precision of the cell under charge to detect the relatively small \( \Delta V\) signature.

The charge profile of an N-700 cell during various charge rates is shown in the figure below.

For fast-charge currents of 1C and larger we can expect to see a negative \(\Delta V\) signature at approximately 110 % charge. At a 1C rate, 110% charge input is a charge duration of 66 minutes.

In order to mitigate ESR of test leads and the batter holder a 4 wire measurement approach is pursued. A schematic of the test setup is shown in the figure below.

Bench supply \(I_{s1}\) is configured as constant current source of 700 mA. Ammeter \(A_{m1}\) measures the charge current applied to the DUT. Series Diode D protects the DUT from being discharged by the supply if OVP/OCP trips or the supply is misconfigured. Voltmeter \(V_{m1}\) is connected directly to the DUTs terminals with independent sense leads.

Prior to initiating a 1C fast-charge both DUTs were given a 1 mA precharge until the cell potential reached approximately 1.2 VDC.

The charge needed to recover a cell back to its nominal potential of 1.2 VDC was 0.014% C.

Cell voltage and temperature during a 1 C fast charge of DUT A is shown in the figure below.

Fast-charge profile of DUT B is shown in the figure below.

Both cells displayed a similar thermal profile over the course of a fast-charge cycle. A plot of both DUTs temperature during the charge cycle is shown in the figure below.

With the exception of the ambient room temperature rising 1.5 degC between charge cycles, the two DUTs display similar thermal profiles while charging.

Near the end of a 1C charge cycle, \(\approx 60\) minutes, cell temperature beings to increases significantly compared to the previous 60 minutes. The thermal rate of the DUT is shown in the figure below.

Interesting, the largest dT/dt occurs at the beginning of a fast-charge cycle. For these particular DUTs the thermal termination signatures is a positive dT/dt of 0.3 degC/min.

Initial temperature profile of a cell under fast-charge is shown in the figure below.

It is believed the temperature rise is due to self heating of the cell’s DCR.

During the first 60 seconds of fast-charging a strong negative \(\Delta V\) signature is observed. A plot of cell voltage for the first 2.5 minutes of charging is shown below.

In order to not false trigger on a charge termination signature, a hold-off of 2 minutes is required for these DUTs.

Offsetting both charge profiles to 0 V at peak cell voltage is shown in the figure below.

One can observe that the negative \(\Delta V\) signature is fairly small, a decline in cell potential of 3 mV over 10 minutes. For these cells a termination signature of \( \Delta V < 0 \) over few minutes would be ideal. One can also observe small short-term fluctuation in cell potential. Hence measurement of \(\Delta V\) should be done over a time span of 1 minute or greater.

Both cells displayed a large termination profile just after initiating a 1C fast-charge cycle. The largest positive thermal rise \(\partial T/\partial t\) was observed during the first few minutes of charging. The largest decline, negative \(\Delta V/\Delta t\) was observed during the first few minutes of charging. A false termination signal could be observed at the beginning of a charge cycle using either the temperature or voltage termination criterion.

The GP NiCd Handbook also indicates the potential for a false \(\Delta V\) early in the charge cycle:

The most popular quick-charge-termination method

for NiCd batteries is the –dV method. However, after

the batteries have been idled for extended periods

of time, a false –dV signal may occur very early

during the first cycle of charging. This may result in

premature charge-termination.

The raw measurement data from fast-charging two NiCd cells is available as csv files below:

The CSV files are formatted as,

`Timestamp [s],Ichg [A],Vcell [V],Tcell [degC]`

Capacitors \(C_f\) and \(C_s\) are included for completeness, as they do exist as parasitic elements in a real circuit. Parasitic shunt capacitance of \(R_f\) may be on the order of 100 fF. Capacitor \(C_s\) is the sum of routing capacitance (perhaps a few pF) and the input capacitance of the op-amp (perhaps 3 pF to 6 pF).

Applying KCL at the inverting-input terminal of the op-amp yields,

$$ V_x s C_s + \dfrac{V_x -V_o}{R_f} +(V_x – V_o)sC_f = I_{in} $$

$$ V_x \left( sC_s + 1/R_f + sC_f \right) – V_o( 1/R_f + sC_f ) = I_{in} $$

$$ V_x \left( \dfrac{1 + sR_f(C_s + C_f) }{R_f}\right) – V_o( \dfrac{1 + sR_fC_f}{R_f} ) = I_{in} $$

The transfer function of the op-amp is modeled as a single pole, unity gain stable amplifier as,

$$ A(s) = \dfrac{A_{ol}}{1 – s/p_a} $$

Where \(A_{ol}\) is the DC open-loop gain and \(p_a\) is the pole based on the GBWP of the op-amp. Since the input signal is applied to the inverting terminal the gain is negative and equal to,

$$ V_o = – A(s) V_x $$

Rearrange for \(V_x\) as,

$$ V_x = \dfrac{-V_o}{A(s)} $$

Substitution into the KCL eqn as,

$$ \dfrac{-V_o}{A(s)} \left( \dfrac{1 + sR_f(C_s + C_f) }{R_f}\right) – V_o( \dfrac{1 + sR_fC_f}{R_f} ) = I_{in} $$

$$ \dfrac{-V_o}{A(s)R_f} \left( 1 + sR_f (C_s + C_f) + A(s) (1 +sR_fC_f)\right)= I_{in} $$

\begin{align*}

\dfrac{V_o}{I_{in}} &= \dfrac{-A(s)R_f}{ 1 + sR_f (C_s + C_f) + A(s) (1 +sR_fC_f)} \\ \\

&=\dfrac{-A_{ol}R_f}{ \left(1-s/p\right)\left(1 + sR_f (C_s + C_f) +\dfrac{ A_{ol}(1 +sR_fC_f)}{1-s/p} \right)} \\ \\

&=\dfrac{-A_{ol}R_f}{ 1 -s/p + sR_f(C_s+C_f)-\dfrac{s^2R_f(C_s+C_f)}{p_a} +A_{ol} +sA_{ol}R_fC_f} \\ \\

\dfrac{V_o}{I_{in}} &=\dfrac{-R_f}{ 1 + s\left( R_fC_f +\dfrac{R_f(C_s+C_f)}{A_{ol}} – \dfrac{1}{A_{ol}p_a}\right) -\dfrac{s^2R_f(C_s+C_f)}{A_{ol} p_a} } \\ \\

\end{align*}

Assuming the time-constant of \(R_fC_f\) is less than the GBWP of the opamp the transfer function can be approximated as,

$$ \dfrac{V_o}{I_{in}} \simeq \dfrac{-R_f}{ 1 + sR_fC_f -\dfrac{s^2R_f(C_s+C_f)}{A_{ol} p_a} } $$

If we assume the poles are well separated (atleast one decade in frequency) the dominant pole is then approximately,

$$ p_1 \simeq \dfrac{-1}{R_fC_f} $$

The second pole occurs at,

$$ p_2 \simeq \left( \dfrac{A_{ol}p_a}{R_f(C_s+C_f)} \right)\left( -R_fC_f \right) $$

Which is equivalently,

$$ p_2 = \dfrac{-\text{GBWP}}{2\pi}\left( \dfrac{C_f}{C_f + C_s} \right) $$

For the purposes of discussion, consider a prototype trans-impedance amplifier with the following parameters,

\begin{align*}

R_f &= 10 \text{ M}\Omega \\

C_f &= 10 \text{ pF} \\

C_s &= 90 \text{ pF} \\

A_{ol} &= 100 \text{ dB} \\

\text{GBWP} &= 1 \text{ MHz} \\

\end{align*}

The LT-Spice schematic of the sample amplifier is shown in the figure below.

The exact transfer function is then,

\[ \dfrac{V_{out}(s)}{I_{in}(s)}= H(s) = \dfrac{-10^7}{159.2\cdot 10^{-12} s^2 + 100.2\cdot 10^{-6} s + 1} \]

With the exact poles of \(H(s)\) being,

\[ p_1 = -1.615 \text{ [kHz]},\;\;\; p_2 = -98.554\text{ [kHz]}\]

The approximated poles as developed above are the following,

\[ \hat{p_1} = -1.592 \text{ [kHz]},\;\;\; \hat{p_2} = -100\text{ [kHz]}\]

A bode plot of the transfer function of this sample trans-impedance amplifier is shown in the figure below.

]]>A simplified schematic of the test setup is shown in the figure below.

A simple relaxation oscillator is constructed with a CD40106 schmitt-trigger inverter. Bench supply \(V_s\) is stepped programatically from 0 to 20 VDC in 100 mV steps. The output clock signal is probed with a 10x probe to a DS1054Z oscilloscope. The hardware frequency counter in the scope is employed to measure the oscillation frequency. Wave measurement function ‘PDUTY’ is used to measure the duty cycle of the output clock signal. Integration capacitor C1 is probed with a 10x probe to channel 2 of the DS1054Z. Measurement function ‘VMIN’ is employed to measure the negative threshold voltage \(V_N\). Measurement function ‘VMAX’ is employed to measure the positive threshold voltage \(V_P\).

A scope capture of the test oscillator is shown in the figure below. Channel 1 and 2 are connected to the test oscillator as shown in the test schematic above.

The rise/fall time of the CD40106 is quite slow, with a its typical specification being 100 ns @ \(V_{dd} = 5} VDC. A scope capture of a falling clock edge is shown in the figure below. A fall-time of 28 ns when loaded with a 10x probe is better than the specification in the datasheet.

A 10x probe may have a effective input capacitance of 10 pF to 15 pF. Assuming the Cd40106 has a drive strength of approximately 5 mA the rise/fall time driving a capactive load of 50 pF which is limited exclusively by drive strength would be,

$$ t_f = \dfrac{(0.9V_{dd}-0.1V_{dd}) C_L}{I_O} = \dfrac{4 \text{ V} \cdot 50 \text{ pF}}{5 \text{ mA}} = 40 \text{ ns} $$

Contrasting that with the fall-time measured on the test oscillator the drive strength of the output pin would be

$$ I_O = \dfrac{0.8V_{dd} C_L}{t_f} = \dfrac{ 4 \text{ V} \cdot 15 \text{ pF}}{28 \text{ ns}} = 2.1 \text{ mA} $$

A scope capture of the rising edge of the clock signal is shown in the figure below.

The rise time is approximately equal to the fall-time at 29 ns.

$$ R_1 = 9.98 \text{ k}\Omega, \;\;\; C_1 = 230 \text{ pF} $$

The MIN/MAX measurement functions of the DS1054Z are used to measure the threshold voltages as seen by capacitor C1.

The frequency of oscillation versus supply voltage is shown in the figure below.

The DS1054Z appears to only use the 1200 sample point screen buffer for measurement functions, resulting in poor resolution of the duty cycle measurement. The figure below provides the duty cycle of the output clock signal.

From the post: “cd40106-schmitt-trigger-relaxation-oscillator” the two solutions for the oscillation frequency of a schmitt-trigger relaxation oscillator are the following,

$$ f_{RC} = \dfrac{1}{RC \log \left( \dfrac{(V_{dd}-V_N)V_P}{(V_{dd}-V_P)V_N} \right)}$$

$$ f_{constI} = \dfrac{V_{dd}}{4RCV_H} $$

The figure below provides both frequency solutions and the measurement results.

Interestingly, the constant current model still provides reasonable agreement for this particular DUT and R/C combination.

The threshold voltages \(V_N\) and \(V_P\) scale ratiometerically with supply voltage resulting in an approximately constant oscillation frequency from \(V_{dd} = 4\) V to \(V_{dd} = 20 \) V.

From 1.5 VDC to 3 VDC, the oscillator behaves as a linear VCO.

The raw data for the CD40106 relaxation oscillator is provided below.

The CSV file is formatted as,

`Vdd [V],Vn [V],Vp [V],Fosc [Hz],DutyCycle []`